Staff ASIC Design Verification Engineer

Company: Google
Location: Sunnyvale
Posted on: April 2, 2026

Job Description:

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc. Knowledge of general purpose operating systems such as Linux and Android. Familiarity with ARM Instruction Set Architecture. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $192,000-$278,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Lead the functional verification team for significant portions of TPU designs, developing advanced functional verification infrastructure such as subchip, subsystem and fullchip level environments. Define and drive advanced verification strategies, including the use of simulation, for bug hunt, formal verification for corner-case bugs and emulation for large-scale system validation. Perform functional verification and performance validation for both pre-silicon and post-silicon phases. Work closely with front-end design, architecture, and performance teams to ensure architectural compliance and achievement of performance goals. Analyze coverage from various dimensions and develop monitors and checkers for quality assurance.

Keywords: Google, Fairfield , Staff ASIC Design Verification Engineer, Engineering , Sunnyvale, California