Head of Design Verification, Interface IP

Company: Etched
Location: San Jose
Posted on: April 2, 2026

Job Description:

About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. This is a hands-on technical leadership role: you will manage a small team while personally owning DV strategy, execution, and tape-out sign-off for critical subsystems including CPU subsystems, HBM memory controllers, PCIe, Ethernet, and system peripherals. You will lead Interface IP DV from architecture definition through tape-out, working closely with RTL designers, IP vendors, SoC and performance DV, software, and architecture teams. You will set standards, define best practices, and ensure verification quality scales with increasingly ambitious chips. Key responsibilities • Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs • Act as the technical authority on correctness, protocol compliance, performance, and robustness • Lead DV for CPU subsystems (boot, interrupts, coherency, system control) • Lead DV for high-speed interfaces, including throughput and latency verification • Architect and evolve SystemVerilog/UVM verification environments • Drive vendor IP integration, configuration reviews, and verification gap closure • Partner closely with architecture, RTL, SoC DV, and software teams • Hire, mentor, and lead a small, high-impact Interface IP DV team • Advise the strategy and execution of emulation testing for pre-silicon validation You may be a good fit if you have • 10 years of design verification experience with ownership of complex IP or SoC subsystems • Deep hands-on expertise in SystemVerilog and UVM • Strong understanding of SoC mCPU design and high-speed interfaces (PCIe, Ethernet, AXI/AMBA) • Tape-out experience with final DV sign-off responsibility • Systems-level DV mindset • Comfortable being hands-on in a fast-moving startup environment Strong candidates may also have experience with • Experience leading DV teams at Apple, NVIDIA, Broadcom, AMD, or similar • Vendor IP evaluation and integration experience • Exposure to formal verification, emulation, or silicon bring-up • Power-aware or low-power interface verification Benefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Housing subsidy of $2k per month for those living within walking distance of the office Relocation support for those moving to San Jose (Santana Row) Various wellness benefits covering fitness, mental health, and more Daily lunch dinner in our office How we’re different Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Keywords: Etched, Fairfield , Head of Design Verification, Interface IP, Engineering , San Jose, California