Senior RTL Design Engineer
Location: Campbell
Posted on: June 23, 2025
|
|
|
Job Description:
DFX RTL Design Engineer (Specialized) Candidate must be able to
come onsite to San Jose, CA 3 days per week JOB DUTIES: This is a
position for senior level RTL design engineer. As a part of the
design team, candidate will be exposed to several IPs including
Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful
candidates will be participating in the DFX RTL coding/integration
of leading edge I/O SoC in 3 nm processes. This DFX RTL Design
Engineer is expected to contribute in : Implementation of SOC DFT
features (TAP controller, GPIOs, ESD structures etc) into RTL using
Verilog/system verilog Responsible for all RTL checks including
lint/elab/CDC/RDC with 0-waivers SOC level JTAG/IJTAG
implementation (RTL/ICL/PDL) Gate level simulation using Synopsys
VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF
development and hand-off to PD Spyglass bringup and analysis for
scan readiness/test coverage gaps. Candidate will also be engaged
in silicon bring-up and debug as needed. Candidate must have a BS
in EE or CS. MS is a plus.
Keywords: , Fairfield , Senior RTL Design Engineer, Engineering , Campbell, California
